Generally, in an integrated circuit for performing a calculation process based on an operation clock, it is necessary to prepare a large design margin, for fear of unevenness in a manufacturing process, variation in a power source, and variation in temperature, so as to enable the integrated circuit to continuously operate in a normal manner. That is, it is necessary to design the integrated circuit so that: even when a delay time is increased by a various kinds of variation and the like, the whole integrated circuit operates within a single clock. In addition, a sufficiently high power source voltage is applied to the integrated circuit so that the integrated circuit operates even when all the conditions are the worst.
However, the large design margin and the high power source voltage prevent the integrate circuit from operating at a high speed and prevent power consumption from being lowered. Then, there is being developed a technique by which an operational condition of the integrated circuit is detected and the power source voltage is controlled so as to provide a minimum power source voltage required in operating the integrated circuit.
FIG. 13 is a diagram schematically showing a structure of a typically conventional voltage conversion circuit 1 which can vary the power source voltage. The voltage conversion circuit 1 is disclosed in U.S. Pat. No. 6,166,562 (Date of Patent: Dec. 26, 2000). As shown in FIG. 13, the voltage conversion circuit 1 includes a duty ratio control circuit 2, a buffer circuit 3, a filter circuit 4, a critical path circuit 5, a delay circuit 6, a true/false evaluation circuit 7, and an adder 8.
The duty ratio control circuit 2 is a circuit for controlling variation of an output voltage from the buffer circuit 3, and includes a counter 11 and a comparator 12. The counter 11 counts each of numbers from 0 to 2n−1 (for example, 0 to 63 when n=6) for each cycle of a supplied clock signal (not shown), and transmits thus counted number to the comparator 12 as a signal NA of n bit. Note that, the counted number returns from 2n−1 to 0. Further, not only the signal NA but also a signal NB of n bit is inputted from the adder 8 to the comparator 12.
The comparator 12 is a circuit for controlling ON/OFF of a PMOS transistor mp and an NMOS transistor mn that constitute the buffer circuit 3, and the comparator 12 supplies control signals x1 and x2 respectively to gates of the transistors mp and mn. Note that, when the signal NA is 0, the comparator 12 makes voltage levels of the control signals x1 and x2 low, and when the signal NA is equal to the signal NB, the comparator 12 makes the voltage levels of the control signals x1 and x2 high.
In the buffer circuit 3, a first power source voltage (here, VDD) whose level is high is applied to a source of the PMOS transistor mp, and a second power source voltage (here, ground voltage) whose level is low is applied to a source of the NMOS transistor mn. Further, drains of both the transistors mp and mn are connected to each other, and a connection node thereof functions as an output terminal of the buffer circuit 3.
Thus, in case where levels of the control signals x1 and x2 are low, the PMOS transistor mp turns ON, and the NMOS transistor mn turns OFF, so that an output voltage of the buffer circuit 3 is equal to the first power source voltage (VDD). While, in case where levels of the control signals x1 and x2 are high, the PMOS transistor mp turns OFF, and the NMOS transistor mn turns ON, so that the output voltage of the buffer circuit 3 is equal to the second power source voltage (ground voltage). That is, the output voltage of the buffer circuit 3 varies as indicated by a pulsed voltage signal v1 which rises when the signal NA is 0 and drops when the signal NA is equal to the signal NB.
The voltage signal v1 is smoothed by the filter circuit 4 constituted of an inductance 1 and a capacitor c, so as to be an output voltage v2. The output voltage v2 is supplied to internal circuits (not shown) formed on the same substrate, and is used as a driving voltage of the internal circuit. Further, the output voltage v2 is used also as a power source voltage of the critical path circuit 5.
Suppose that: a time in which the PMOS transistor mp constituting the buffer circuit 3 turns ON and the NMOS transistor mn constituting the buffer circuit 3 turns OFF (i.e., a time in which levels of the control signals x1 and x2 are low) is an ON time T1, and a time in which the PMOS transistor mp turns OFF and the NMOS transistor mn turns ON (i.e., a time in which levels of the control signals x1 and x2 are high) is an OFF time T2, it is possible to calculate the output voltage v2 of the filter circuit 4 in accordance with the following expression.v2=(T1/(T1+T2))×VDD  (1)
Here, the ON time T1 (numerator of the right side) in the expression indicates a pulse width of the voltage signal v1, and T1+T2 (denominator of the right side) which is a total of the ON time T1 and the OFF time T2 indicates a pulse cycle of the voltage signal v1. That is, in order to control a minimum power source voltage required in operating the integrated circuit in which the output voltage v2 is desired, a ratio of the voltage signal v1's pulse width and pulse cycle (hereinafter, referred to as duty ratio) is controlled.
Then, in the voltage conversion circuit 1 arranged in the foregoing manner, a value of the signal NB inputted from the adder 8 to the comparator 12 is varied, so that the ON time T1 (pulse width) is varied, thereby controlling the duty ratio of the voltage signal v1 outputted from the buffer circuit 3. Thus, it is possible to control the driving voltage (output voltage v2) supplied to the internal circuits. Hereinafter, such duty ratio control system is referred to as a pulse width variation system. Further, as means for setting the signal NB to a most appropriate value, there is adopted a method in which an operation speed of the critical path circuit 5 is detected.
The critical path circuit 5 is a circuit obtained by copying a path circuit whose signal is delayed for the longest time in the internal circuits. As described above, as the power source voltage, the output voltage v2 of the filter circuit 4 is applied to the critical path circuit 5. That is, a driving voltage of each internal circuit to which the power source is supplied is monitored by the critical path circuit 5. Here, the description is given on the assumption that an operable voltage of the critical path circuit 5 is an operable voltage of the internal circuit.
In case where the critical path circuit 5 is operable due to the output voltage v2 of the filter circuit 4, the critical path circuit 5 transmits predetermined data to the true/false evaluation circuit 7. At this time, the data transmitted from the critical path circuit 5 is directly inputted to the true/false evaluation circuit 7, and delay data obtained by causing the delay circuit 6 to delay the data by a predetermined time is also inputted to the true/false evaluation circuit 7.
In case where the data is not directly inputted from the critical path circuit 5 to the true/false evaluation circuit 7, the true/false evaluation circuit 7 judges that the targeted internal circuit does not normally operate, that is, the true/false evaluation circuit 7 judges that the driving voltage of the internal circuit (output voltage v2 of the filter circuit 4) is too low. Then, the true/false evaluation circuit 7 transmits a signal s1, which increases the value of the signal NB so that its increment is only 1 so as to increase the driving voltage v2, to the adder 8.
While, in case where the delay data is inputted to the true/false evaluation circuit 7 via the delay circuit 6, the true/false evaluation circuit 7 judges that the internal circuit normally operates even when the signal is delayed, that is, the true/false evaluation circuit 7 judges that the driving voltage of the internal circuit is too high. Then, the true/false evaluation circuit 7 transmits a signal s2, which decreases the signal NB so that its decrement is only 1 so as to decrease the driving voltage, to the adder 8.
Moreover, the data is directly inputted from the critical path circuit 5 to the true/false evaluation circuit 7. However, in case where the delay data that has passed through the delay circuit 6 is not inputted, the true/false evaluation circuit 7 judges that a most appropriate driving voltage is applied to the targeted internal circuit, so that the true/false evaluation circuit 7 does not transmit the signals s1 and s2.
In case where the signal s1 is inputted from the true/false evaluation circuit 7, the adder 8 supplies a signal, obtained by adding 1 to the present value of the signal NB, to the duty ratio control circuit 2. While, in case where the signal s2 is inputted from the true/false evaluation circuit 7, the adder 8 supplies a signal, obtained by subtracting 1 from the present value of the signal NB, to the duty ratio control circuit 2.
In the voltage conversion circuit 1 arranged in the foregoing manner, the critical path circuit 5, the delay circuit 6, and the true/false evaluation circuit 7 detect the operation speed of the internal circuits to which the power source is supplied, and control the duty ratio of the voltage signal v1 so as to decrease the driving voltage (output voltage v2) of the internal circuits when the detected operation speed is too fast, and so as to increase the driving voltage of the internal circuit when the detected operation speed is too slow.
As described above, the voltage conversion circuit 1, disclosed by U.S. Pat. No. 6,166,562, which uses a circuit for detecting the operation speed of the critical path circuit 5 and the duty ratio control circuit 2, allows the output voltage v2 to vary in a wide range, so that the voltage conversion circuit 1 is useful as a step-down circuit for decreasing a voltage of a general integrated circuit. However, this structure raises such a problem that: a size of a circuit required in controlling the adder 8 or the like which enables the output voltage v2 to vary in a wider range is larger. This results in increase in the size of the whole step-down circuit. As a result, power consumption of the step-down circuit itself is increased.
Further, the counter circuit 11 used to control the duty ratio operates at a frequency 64 times a frequency of the voltage signal v1, so that power consumption of the counter circuit 11 itself is high.
Generally, in case where the power source voltage of the internal circuit is low or a load current is small, the power consumption of the whole integrated circuit is small, so that a ratio of the power consumption of the step-down circuit itself becomes relatively large. Thus, it is necessary to reduce the power consumption of the step-down circuit itself, so that the step-down circuit based on the foregoing technique is disadvantageous in case where the internal circuit is operated by a low power source voltage.
In view of the foregoing points, the present inventors devised a step-down circuit, suitable for lowering the output voltage, whose circuit size and power consumption are reduced. This structure is disclosed in U.S. Pat. No. 6,617,898 B2 (Date of Patent: Sep. 9, 2003). A voltage conversion circuit 21 of U.S. Pat. No. 6,617,898 B2 is shown in FIG. 14. In FIG. 14, the same reference signs are given to members corresponding to members of FIG. 13, and description thereof is omitted.
The voltage conversion circuit 21 supplies the output voltage v2, outputted from the filter circuit 4, as a power source voltage of the output pulse signal generating circuit 22 and the switch timing control circuit 23. Further, the voltage conversion circuit 21 includes not only the output pulse signal generating circuit 22 and the switch timing control signal 23, but also the buffer circuit 3, the filter circuit 4, and step-up level shifters 24 and 25.
The output pulse signal generating circuit 22 is constituted of the reference pulse signal generating circuit 26, the delay circuit 27, and the delay time control circuit 28. Not the external power source voltage VDD but the output voltage v2 of the filter circuit 4 is supplied to each of the circuits 26, 27, and 28 of the output pulse signal generating circuit 22 and the switching timing control circuit 23 as a power source voltage.
However, when the switch timing control circuit 23 is driven by the output voltage v2 transmitted from the filter circuit 4, each of high level control signals Φ1 and Φ2 for respectively driving the transistors mp and mn corresponds to the output voltage v2, so that a trouble may occur in controlling ON/OFF of the transistors mp and mn. Then, in order to increase voltage levels of the control signals Φ1 and Φ2 to necessary levels, the step-up level shifters 24 and 25 are provided on output stages of the switch timing control circuit 23.
In this manner, all the circuits except for the switch circuit 3 and the filter circuit 4 are driven by the output voltage v2 lower than the external power source voltage VDD, so that it is possible to largely reduce the power consumption of the voltage conversion circuit 21 itself, and it is possible to reduce the power consumption of the whole integrated circuit.
According to the foregoing conventional technique, it is necessary to operate the voltage conversion circuit so as to obtain the output voltage v2, but the existing structure raises such a problem that an output voltage suitable for operating circuits cannot be necessarily obtained on start-up without fail.